A basic phase locked loop (PLL) has a phase detector which provides a phase detect output signal indicative of the phase difference between a loop clock signal and a reference clock signal. The phase detector provides the phase detect output signal to an input of a loop filter. The loop filter is a lowpass filter which provides an output voltage level indicative of the length of time the phase detector detects the two clock signals are out of phase. The output of the loop filter drives an input of a voltage controlled oscillator (VCO). The VCO then provides a clock output signal having a desired frequency. The clock output signal is divided in a loop divider to provide the loop clock signal. Thus, the PLL is able to generate the clock output signal having a frequency that is many times greater than that of the reference clock signal, based on the value of the loop divider.
In a digital implementation, a phase detector provides a digital output to indicate a phase difference between the two input clock signals. For example, a three-state phase detector may provide a single output signal in a logic high state to indicate a leading phase between the reference clock signal and the loop clock signal, in a logic low state to indicate a lagging phase, and in a high impedance state to indicate a lock condition. Another type of digital phase detector, known as a type IV phase detector, provides one output signal in an active logic state, such as a logic high, to indicate the leading phase between the reference clock signal and the loop clock signal. The type IV phase detector also provides a second output signal in the active logic state to represent the lagging phase between the reference clock signal and the loop clock signal. The type IV phase detector provides both output signals in an inactive logic state to indicate the lock condition.
The digital loop filter then samples the output of the phase detector at a relatively high rate to accurately detect the amount of time the signals are out of lock. The loop filter provides a digital code based on the current and prior value of the samples. This type of PLL presents an inherent tradeoff between power consumption and sensitivity to clock jitter. If the loop filter samples the output of the phase detector at a relatively high rate, it more accurately represents the phase difference, and thus the PLL provides the clock output signal with low jitter. However, the high sampling rate increases power consumption. If the loop filter's sampling rate decreases, power consumption decreases but clock output signal jitter increases.
Another problem is that the digital phase detector circuit itself may cause unwanted signal jitter. When the loop clock signal is essentially locked to the reference clock signal, there may still exist some relatively-small phase difference between the two signals, such as a few nanoseconds (ns). However, the phase detector may be unable to accurately differentiate a difference this small. Thus, the phase detector's output on a transition of the clock signals is indeterminate and does not accurately reflect the actual phase difference. This results in increased signal jitter. A PLL which has both relatively-low power consumption and relatively-low clock output signal jitter would therefore be desirable.